Process for controlling the correct positioning of test probes on terminations of electronic devices integrated on a semiconductor and corresponding electronic device

ABSTRACT

An embodiment for making a check of the electric type executed on wafer for testing the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on semiconductor wafer. An embodiment consists in making a current circulate in at least part of the seal ring of at least one of the above devices, and in case it has to flow in the seal ring of more devices, these seal rings are suitably interconnected to each other. Thanks to an embodiment the seal ring may also be reinforced in the angle areas of the chip, and suitable circuits may be possibly inserted in the seal ring or between the seal rings.

PRIORITY CLAIM

The instant application claims priority to Italian Patent ApplicationNo. MI2009A002332, filed Dec. 30, 2009, which application isincorporated herein by reference in its entirety.

TECHNICAL FIELD

An embodiment relates to a method for checking the correct positioningof test probes on pads of electronic devices integrated on asemiconductor.

An embodiment also relates to an electronic device integrated on asemiconductor wafer and equipped with means for the actuation of theabove method.

An embodiment may be applied, in particular, to the process of electricselection of the wafers or testing EWS (Electrical Wafer Sort or more ingeneral Wafer Sort) or for the WLBI (Wafer Level Burn-In) i.e. electrictesting that executes the test (also in temperature) with stress on thedevices subjected to the test.

BACKGROUND

As it is known in this specific technical field, for the final qualitycheck, a process of electrical sorting of the semiconductor electronicdevices is carried out by executing a testing EWS directly on wafer. Tothis aim it is often necessary to electrically connect a testingapparatus, called tester ATE, that executes the measures on the devicesof the wafer.

This situation is schematically shown in FIG. 1.

Between the apparatus ATE and the wafer 1 there is an interfacecomprising a probe card 2 having an end 3 (probe head) with which alsoseveral hundreds (or thousands) of probes 4 are associated thatelectrically connect the ATE to the almost totality of the pads of thedevices to be tested.

In general the wafer is positioned on a support 5 called chuck belongingto an apparatus called prober.

In consequence, the probes 4 of the ATE should be temporarily connectedto all the pads 6 of the electronic device to be tested, as shown inFIG. 2, or of the devices since the testing in parallel of severalelectronic devices simultaneously is more and more frequent.

The number of probes 4 of the resources necessary for the testing mayalso be smaller or identical to the number of pads 6 present on thedevice.

In a similar way checks are carried out also on integrated circuits forwhich it is necessary to contact the respective bumps.

Within this domain it may be very important that the generic probe 4 iswell centred on the corresponding pad 6.

Last generation electronic devices have a very high number of pads to becontacted which have a more and more reduced area and are often veryclose to each other.

In particular the more a pad has a small size, the more probable thebreakage of the passivation surrounding the pad is further to a noncorrect contact by the relative probe.

It may be very important that all the probes are planar with each otheron the vertical axis Z and have a high alignment with respect to thehorizontal plane XY. This allows to reduce the damaging problems of thepad and breakages of the passivation.

At present the testing in production of the correct alignment betweenthe generic probe and the pad may be made by observing the signs thatthe probe leaves on the pad after having contacted it, but this checkoccurs after having executed the testing step and is not preventive.

FIGS. 3B to 3D show examples of signs left on a pad by the non correctpositioning or alignment of a test probe.

The testing operation may, however, be executed on the prober in amanual way or in an automatic way.

Apparatuses also exist that are different from the prober that test thealignment and the planarity of the probes of the probe card.

However, recently, for meeting the growing requests of electronicapplications able to sustain higher and higher temperatures, newmaterials have been introduced for realising the end pads of theelectronic circuits and for the connections between these pads and thesubstrate of the package, which is the container of the circuit, so asto ensure a good electric connection.

Some of these materials for the pads are also used to strengthen the paditself and in consequence these materials have a greater hardness thanthe materials traditionally used like the aluminium.

This implies that the signs left by the probe may not always be seen onthese particular hard materials, even after different mechanical actionsof contacting of the probes on the pads.

In consequence, a check in production of the correct centring of theprobes on the pads may become difficult, requiring long times and withconsequent breakage problems of the passivation that implies theproduction performance loss with a consequent economic damage.

The adoption of pads realized with hard metals thus may make itdifficult to execute a process of reliable probing and in consequence itis possible to lose production electric performance with a consequentincrease of the costs.

Production problems are added to all this, these problems furtherburdening the costs in case, for example, testing problems of anon-immediate solution arise, such as for example a bad electric contactbetween the probe and the pad.

SUMMARY

An embodiment is a process for checking the correct positioning of testprobes on pads of electronic devices integrated on semiconductor havingsuch functional characteristics as to allow to execute this check in acompletely automatic way and by means of an electric testing, devicesprovided with pads realized with hard metals being also present.

An embodiment is based on the assumption that it is not possible tovisually value the correct alignment between a generic probe and itscorresponding pad; therefore, it has been thought to execute a check ofthe probing process counting on a methodology of the electric type.

An embodiment for checking the correct positioning of test probes onpads of electronic devices integrated on semiconductor wafer, in which aplurality of said probes associated with an interface of a testingapparatus are guided mutually approaching and departing from said padsof the electronic device/s for executing quality checks based onelectric tests, includes at least one control probe chosen in saidplurality of probes being put into contact with a correspondingadditional control pad of the device subjected to the testing forexecuting a preliminary electric test and deriving an estimate ofalignment or correct positioning of the other probes with thecorresponding pads.

The preliminary electric test and contact step may be executed by meansof a pair of control probes on a corresponding pair of additionalcontrol pads.

The control probes may be put into contact with the additional controlpads prior to other probes and simultaneously with them.

The probes of said pair of control probes may be put across saidplurality of probes or in positions being considered as critical inrelation to the specific application so as to better detect a possibledrift of the correct alignment of positioning.

Moreover, the electric test may provide the application of a currentflow that crosses said pair of control probes; this electric test may befollowed by means of a test circuit housed in a seal ring region of theelectronic device.

An embodiment also relates to a semiconductor electronic deviceintegrated with other devices on a substrate of a semiconductor waferand comprising electric connection pads also intended for being contactsby a plurality of probes associated with an interface of a testingapparatus for quality checks based on electric tests, comprising atleast one additional control pad specifically provided for beingcontacted by a control probe chosen among probes for executing apreventive electric test and deriving an estimate of alignment orcorrect positioning of the other probes.

The electronic device may comprise at least one pair of additionalcontrol pads arranged on opposite parts of said device.

More in particular, said additional control pads may be arranged onopposite angular regions of the electronic device.

Moreover, said additional control pads may be placed outside a seal ringdelimiting, with respect to one another, said devices on said wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

Characteristics and advantages of a process and of a device according toone or more embodiments will be apparent from the following descriptiongiven by way of indicative and non limiting example with reference tothe figures of the annexed drawings.

FIG. 1 shows a schematic view of a wafer whereon semiconductorelectronic devices are realized subjected to final quality checks bymeans of an interface of a testing apparatus ATE;

FIG. 2 shows a schematic view of an electronic device contacted by aplurality of probes of the interface of FIG. 1;

FIG. 3A is a schematic, enlarged view form above of tracks left by acorrect contact of test probes on pads of an electronic device to betested;

FIGS. 3B to 3D are respective schematic, enlarged views from above oftracks left by a wrong contact of test probes on pads of an electronicdevice to be tested;

FIG. 4 shows a schematic view from above of a semiconductor wafer and ofan interface of a testing apparatus ATE as modified according to anembodiment;

FIG. 5 shows a perspective, schematic view of an electronic deviceintegrated on semiconductor and incorporating additional control padsaccording to an embodiment;

FIG. 6 shows a schematic, enlarged view from above of a group ofelectronic devices adjacent to each other on a semiconductor waferaccording to an embodiment;

FIG. 7 shows a schematic, enlarged view from above of an electronicdevice and of the near structures according to an embodiment;

FIGS. 8 and 9 are further schematic, enlarged views from above of thegroup of devices of FIG. 6 according to an embodiment;

FIG. 10 shows a perspective, schematic view of the group of electronicdevices of FIG. 9 incorporating two additional control pads according toan embodiment;

FIGS. 11A, 11B and 12 show respective schematic views of enlargeddetails of some electronic devices integrated on semiconductor wafer andstructured according to an embodiment;

FIG. 13 shows a schematic view from above of a semiconductor wafer andof an interface of a testing apparatus ATE modified according to afurther embodiment;

FIGS. 14 to 21 are respective schematic, enlarged views of angularregions of near electronic devices on the wafer of FIG. 6 and relativeto different embodiments;

FIGS. 22 to 25 are respective schematic, vertical section views ofdetails of an electronic device according to an embodiment;

FIGS. 26 and 27 are respective schematic views of alternativeembodiments of a device.

DETAILED DESCRIPTION

With reference to these figure, and in particular to the examples ofFIG. 4 and following ones, 10 globally and schematically indicates asemiconductor wafer whereon several electronic devices 11 are integratedaccording to an embodiment. These devices 11 are arranged in an orderlyway on the wafer and delimited with respect to one another bydemarcation lines 12 so called scribe lines.

Each electronic device 11 may be electrically contacted by means of aplurality of peripheral pads 13, in contact to which probes 4 of aninterface 2 or probe card are guided mutually approaching and departing,the probe card being associated with a testing apparatus ATE, thislatter being not shown since conventional.

As explained above, the presence of very hard pads 13 makes it difficultto identify a sign due to the contact of a probe 4 and, in consequence,it is difficult to value visually and in an easy way if the probing andtesting process is occurring correctly.

In these circumstances it may be probable that breakages occur in thepassivation protective layer that covers the electronic devices 11 to betested; and devices with the broken passivation layer may have to bediscarded.

According to an embodiment it has been provided that at least onecontrol probe 24 chosen in the group or array 22 of probes 4 of theinterface 15 is put into contact with an additional control pad 16connected to a test circuit 17 associated with or internal to thecorresponding device 11 through which a test procedure will test thecorrect contacting of the probe 24 on the pad 16. On the basis of theresult of this check, information will be derived about the fact thatthe contacting or probing process does not have serious drifts, i.e.that the process is under control.

Considering a generic array 22 of probes 4 of a probe card 2 that areintended for contacting at least one device 11 of the wafer 10, it hasbeen thought to use, for example, at least two control probes 24, 25that may be placed at the ends of the array 22 of the probes 4 so as tobe more sensitive and thus better detect a drift of the probing process.

In fact if the probing process has a drift, in general it will be moremarked at the ends of the array 22 with respect to the other regions ofthe array 22 of probes 4.

The two control probes 24, 25 are suitably connected to two respectivecontrol pads 16, 18 belonging to at least one same device 11 on thewafer 10.

Moreover, for housing the test circuit 17 of the probing process, aportion of the wafer called a seal ring 20 (FIG. 6) may be, for example,used to which said two control pads 16, 18 will be connected. Throughthe seal ring 20 a current will be made flow during the test step. Theflow of this current will supply the information that the probingprocess does not have a drift to be considered as dangerous.

For completeness of the description and for better understanding all theaspects of an embodiment, it is now suitable to illustrate more indetail the edge structure of the electronic devices 11 integrated on thewafer 10; this will be made with reference to FIGS. 6 and 7.

After an electric testing step of the various devices 11 present on thewafer 10, they are separated from each other through a conventionalcutting operation of the wafer itself by means of the blades of a saw ora laser ray.

The electronic devices 11 being realized on the wafer 10 are normallyalready delimited with each other by a so called scribe line 12 thatrepresents also the interstice whereon the cutting means that physicallyseparate the devices during the cutting operation act. FIG. 7 shows anenlarged view of this scribe line 12.

The scribe lines 12 are often exploited also for introducing elementalstructures 21 or TEG (Test Element Group) intended for the testing ofsome process parameters, that are measured in general prior to theelectric test on wafer, as shown in FIG. 6.

To protect the electronic devices 11 from the mechanical actionsexercised by the blade during the cutting, each device 11 isperipherally surrounded by a so called seal ring 20 that has the aim ofsealing the device 11 itself and strengthening it mechanically forensuring the reliability also after the cutting.

The seal ring 20 is put in general between the area where the pads 13are placed, or pad ring of the device 11, and the scribe line 12 thatsurrounds the device 11 itself.

The seal ring 20 is formed with more metallic layers and vias and alsoserves for blocking ions and contaminative substances too that canjeopardize the good operation of the device 11.

Several implementations of seal ring are however known, where forexample dielectric layers and metallic layers are alternated.

Sometime for avoiding problems of interferences in radiofrequency, openloop seal rings are realized instead of closed loop ones so as to avoidthat the seal ring behaves like a coil.

The angles of the seal ring 20 may be the most critical regions and theyare usually reinforced, for example, by using metals of greater size andpossibly rounded off/smoothed.

Situations are also known in which at the angles of the seal ring 20there are suitable patterns of structures that avoid the damaging of theangles of the seal ring itself.

An embodiment also provides that the additional pads 16, 18 may besuitably positioned outside the seal ring 20.

More in particular, these additional pads 16, 18 may be realized incorrespondence with opposite angular regions of the electronic device 11outside the seal ring 20, which in correspondence with these oppositeangular regions is deviated to form substantially a part of a polygonalpath.

With this structure it may be possible to execute a preventive test tocheck the correct alignment of the probes before starting with theelectric test for checking the correct operation and the quality on agiven electronic device contacted by the array of probes 4.

For example, by first exploiting the additional pads 16, 18 with thecorresponding control probes 24, 25 it may be possible to make a currentcirculate through these two control probes 24, 25. If this current doesnot circulate correctly, this means that there is a drift of the probingprocess due to for example to probe—pad alignment problems, or thatthere are problems of electric continuity or other.

To make this initial check more sensitive, the above two control probes24, 25 may be subjected to a stress being identical or greater than thestress to which the generic probe 4, which is considered the morecritical than the array 22 of probes, is subjected.

For example if there are probes 4 crossed by high currents during thetest of at least one device, a current will be made to circulate beingidentical or greater in the control probes 24, 25 of the probing processwith respect to the most critical probe 4 during the test of that givendevice; in this way the drift of the probing process may be detected inadvance.

The two additional pads 16, 18 intended for the check of the alignmentmay also have smaller size with respect to the other pads 13 of thedevice, so as to make the check even more sensitive.

Moreover, if these two additional pads 16, 18 are placed outside theseal ring 20 there may also be the advantage of not increasing the areaof the device.

It is to be noted that the presence of the additional pads 16, 18 onopposite angles of the device 11 may confers a greater strength of theseal ring 20 that passes nearby, indirectly protecting this angle of thedevice during the cutting of the wafer.

All these considerations may be naturally extended to the case ofsimultaneous testing of more devices in parallel.

To facilitate the testing in parallel it has been thought to addsuitable interconnection structures 23 (FIG. 9) that connect to eachother at least two additional pads 16, 18 placed in two borderingangular regions near two distinct seal rings 20.

As shown in FIGS. 8 and 9 these interconnection structures 23 may beextended only to the angular regions 15 of adjacent devices and, beingnear the seal ring 20, they do not interfere with the TEG 21 placed inthe scribe lines 12 of the wafer 10.

With the above described measure, a test current may be made tocirculate between at least two devices 11 placed on the wafer 10although applying the sole two probes 24, 25, as shown in FIG. 10.

The interconnection structure 23 may be realized by means of at leastone metallization track that will pass through the scribe line 12 orabove the same.

The use of at least two metallization levels connected by at least onevias, for realizing the interconnection 23, may allow reducing thestress that the seal ring 20 will sustain when this interconnection 23is cut by cutting means that physically separate the devices 11 duringthe cutting operation.

Suitably, a control pad 27 may be provided on the interconnectionstructure 23 being substantially positioned between the borderingangular regions of two devices 11, as shown in FIG. 11A.

In general these structures may be positioned also along the scribe line12 as shown in FIG. 11B according to the application.

As shown in FIG. 12, also plural control pads may be provided, forexample a pair of pads 28, 29, arranged on the interconnection structure23 between two bordering angular regions, so as to make the electriccheck of the probing process more sensitive.

To facilitate the testing operations provided by the process of anembodiment it may be possible to equip the probe card 2 connected to thetesting apparatus ATE with control probes placed in any angle of thearray of probes 4; for example, FIG. 13 shows a rectangular array 22 ofprobes with four control probes 24, 25, 26 and 31 arranged in thecorners.

It may also be possible to have a control pad 16, 18, 28, 29 for eachcorner of the device, and each corner may be electrically connected tothe corners close to it, as shown in FIG. 14.

A plurality of control pads may be present and suitably positioned so asto have control probes not only in the angles/corners of the array 22but for example along its perimeter so as, for example, to have moretypes of alarm.

Possibly, the control probes may also be far from the array of probes 22due to constructive problems of the probe card 2, or for increasing thecheck sensitivity.

In case test circuits 17 devoid of closed coils are to be realized, forexample for avoiding radiofrequency problems, the structure may becomplicated a little by integrating suitable circuits. For example, asshown in FIG. 15, it is possible to integrate at least one diode D onthe interconnection structure 23 between control pads 16, 18 or 28, 29.This allows making at least one path through which the current flowsunidirectional, as shown in FIG. 15.

For example as shown in FIG. 15 or 16 by connecting the four angularregions of four adjacent devices two diodes D will be positioned, and byrigidly repeating this structure, also according to the design of theseal ring that is an open loop one, the creation of coils will beavoided, however allowing that the current can have at least onepossible path between the at least two control probes 24, 25 or 26, 31.

The control pads may have a circular form so that the check does notdepend on the different orientation of the control probes, as shown inFIG. 17.

Now, with reference to FIGS. 18 to 21 embodiments are shown in which thecontrol pads 35 are realized inside the single electronic device 11,they may thus increase the area of the device itself with a consequentslight increase of the costs.

In this case it may be suitable to connect to each other at least twoadjacent seal rings 20 for allowing the testing in parallel of at leasttwo devices 11, as shown in FIG. 18 with the interconnection lines 33.

If this connection occurs between two angular/corner regions of thedevice, the generic angle 34 of the seal ring 20 may be advantageouslystrengthened so that it is less likely to be damaged by the cutting ofthe wafer, as shown in FIG. 19.

It may thus be advantageous to reduce, as much as possible, the sizes ofthe connection metals so as to facilitate the cutting process of thewafer by using, for example, at least two metal levels and at least onevia as discussed for the connections 23 of FIGS. 9 and 10, but howeverthis has a general validity considering the connections between the atleast two seal rings 20 of at least two different devices 11.

However, several forms of connections are possible between at least twoadjacent devices 11 incorporating in their interior the control pads 35.

Nothing forbids providing several control pads 35 for each device 11 andnot necessarily in the angles of the seal ring 20, according to theapplication, as shown in FIG. 21.

By increasing the number of control pads 35 the arising of false alarmsmay be reduced, and also different levels of severity of the alarms maybe attained.

The various seal rings may be connected to each other in various ways,for example as shown in FIG. 20 and not necessarily in the angles of thesame seal ring, as shown in FIG. 21.

In the example of FIG. 20 if one of the connections between two sealrings 20 is faulty, for example it has a non desired interruption, theother connections between the other seal rings 20 will however allow theelectric check of the position of the probes.

By incorporating these control pads directly in the seal ring 20 it maybe avoided that they may be internal to the device and it is avoidedthat they may hinder the circuits 21 of the TEG, if these control padsare housed for example inside the scribe line 12, as shown in FIG. 21.

This depends on the circuits 21 of the TEG and on which probes of theprobe card they tend to drift earlier during the probing and testingprocess.

The generic control pad may be thus housed or even be part of the sealring 20. Also the mirrored structure or suitable modifications thereof,for example further to rotations may be valid.

A diode may be realized, for example, through a junction PN 37 in thesubstrate 36 of the wafer 10 between the seal ring 20 and the metal pathof the interconnection structure 23, as shown in FIG. 22.

In FIG. 22 and in the following ones, the place of the P doped materialand of the N doped material may be exchanged, according to the circuitthat is to be implemented, according to the dopant of the substrate 36and according to specific design needs. With respect to the scribe line12, also the placement of the seal ring 20 with the metal path may bechanged, as shown in FIG. 23.

Also the control pad outside the seal ring 20 may be added, asschematically shown in FIG. 24.

The control pad 35 may be formed on the same seal ring 20, possiblylocally increasing its size, as shown in FIG. 25.

Moreover, where the seal ring 20 is interrupted for avoiding thecreation of coils, reinforcement mechanical structures may be placed, asshown in FIG. 26.

For example interdigited structures may be realized, that may be usedalso for their capacitive behaviour, and thus for the check of theprobing process a radiofrequency signal may be made to circulate in theseal ring 20, this may be advantageous if for example the most criticalprobe of the array 22 is a probe for radiofrequency signals.

Alternatively, in the seal ring 20 suitable structures may be formed forsignals RF.

Thanks to the at least two control pads 16, 18 connected to the sealring 20, the seal ring may be possibly divided into more parts fortransporting signals and supplying to circuits connected to the sealring itself.

In consequence, in general circuits may be connected to the seal ring,for example those shown with 40 and 41 in FIG. 27. The circuit 40 maybe, for example, formed by at least one diode that may be used for theprobing process check and through which the current necessary for theneeded tests flows.

The presence of the diode may allow to identify the problems of contactresistance between the probe and the pad thanks to a suitable test thatmeasures some characteristics of the diode from which information on thecontact resistance may be derived.

The circuit 41 may be used for different aims and supplied through acurrent that comes from the device 11 or through the control pads 16, 18making a current circulate being opposite to the direction of the diodeof the circuit 40 that will thus be akin to an open circuit.

This circuit 41 may be advantageously used, for example, for containingin a memory useful production data such as the number of lot, the numberof the wafer and the coordinates XY of the device on the wafer.

In consequence these control pads 16, 18 may remain on the device 11 andbeing not removed by the cutting of the wafer and being used againafterwards, for example during the analysis of the failure of the deviceindicated by a client.

The circuit 41 may also be an interface, for example serial, towards theBIST circuits of the device, and thus these control pads 16, 18 may beused also for the test of the device itself.

Moreover, the elemental structures, the circuits and the methodologydescribed may be possibly and advantageously adapted also forincorporating some structures of the TEGs for parametric measures of thetechnological process.

For example, the system in one of its implementations may have a longmetallic path between two control pads being enough far from each other,and this may for example allow to obtain a measure of the resistance ofthis metallic path.

It is possible to provide also an index of contact problems between theprobe and the pad.

An embodiment makes it possible an electric check of the probing processof the wafer.

Moreover an embodiment of a structure allows to strengthen the deviceduring the cutting step of the wafer 10.

Moreover the seal ring 20 may be used also as a circuit element of thedevice itself.

Moreover it may be possible that the current for the check of theposition of the probes instead of flowing between two pads 16 and 18,flows for example between the substrate 36 and the pad 16, and thiscurrent will be injected, for example, through the chuck 5 of the proberin electric contact with the substrate 36. Also a vice versa case may bevalid.

The seal ring 20 or at least part of the same may have the possibilityto be electrically insulated or not by the substrate 36 of the wafer 10according to the specific circuit that is to be realized, according tothe various design ties of the specific device 11 considered.

Naturally for meeting incidental and specific needs, a technician of thefield will have the possibility to apply several modifications to thepreviously described embodiments. It is clear that several omissions,substitutions, and modifications in the form and in the details, asother embodiments are possible; it is also expressly intended thatspecific elements and/or process steps described in relation to anyembodiment of the invention described may be incorporated in any otherembodiment as general aspect of design choices.

An embodiment of an integrated circuit described above may be aprocessor, and may be coupled to another integrate circuit (e.g., aprocessor) to form a system.

From the foregoing it will be appreciated that, although specificembodiments have been described herein for purposes of illustration,various modifications may be made without deviating from the spirit andscope of the disclosure. Furthermore, where an alternative is disclosedfor a particular embodiment, this alternative may also apply to otherembodiments even if not specifically stated.

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 13. An integrated-circuit die, comprising: afirst conductive pad; and a second conductive pad operable to indicatewhether a probe tip is aligned with the first conductive pad.
 14. Theintegrated-circuit die of claim 13, further comprising: a circuit; andwherein the first conductive pad is coupled to the circuit.
 15. Theintegrated-circuit die of claim 13 wherein the first conductive pad isinoperable to show visible evidence of having been contacted by a probetip.
 16. The integrated-circuit die of claim 13 wherein the firstconductive pad is formed from a material that does not significantlydeform in response to contact by a probe tip.
 17. The integrated-circuitdie of claim 13 wherein the first conductive pad is larger than thesecond conductive pad.
 18. The integrated-circuit die of claim 13,further comprising: a region; a seal ring partially surrounding theregion; and wherein the first conductive pad is located inside of theregion.
 19. The integrated-circuit die of claim 13, further comprising:a region; a seal ring partially surrounding the region; and wherein thesecond conductive pad is located inside of the region.
 20. Theintegrated-circuit die of claim 13, further comprising: a region; a sealring partially surrounding the region; and wherein the second conductivepad is located outside of the region.
 21. The integrated-circuit die ofclaim 13, further comprising: a periphery; a seal ring disposed in aportion of the periphery; and wherein the second conductive pad islocated over the seal ring.
 22. The integrated-circuit die of claim 13,further comprising: a periphery; a seal ring disposed in a portion ofthe periphery; and wherein the second conductive pad is located underthe seal ring.
 23. The integrated-circuit die of claim 13, furthercomprising: a periphery; a seal ring disposed in a portion of theperiphery; and wherein a portion of the second conductive pad is commonto the seal ring.
 24. The integrated-circuit die of claim 13, furthercomprising: a corner; and wherein the second conductive pad is locatedapproximately in the corner.
 25. The integrated-circuit die of claim 13,further comprising a third conductive pad operable to indicate whetherthe probe tip is aligned with the first conductive pad.
 26. Theintegrated-circuit die of claim 13, further comprising a thirdconductive pad that is smaller than the first conductive pad and that isoperable to indicate whether the probe tip is aligned with the firstconductive pad.
 27. The integrated-circuit die of claim 13, furthercomprising a third conductive pad coupled to the second conductive padand operable to indicate whether the probe tip is aligned with the firstconductive pad.
 28. The integrated-circuit die of claim 13, furthercomprising: a third conductive pad operable to indicate whether theprobe tip is aligned with the first conductive pad; and a conductorcoupled between the second and third conductive pads.
 29. Theintegrated-circuit die of claim 13, further comprising: a thirdconductive pad operable to indicate whether the probe tip is alignedwith the first conductive pad; a conductor coupled to the secondconductive pad; and a diode serially coupled between the conductor andthe third conductive pad.
 30. The integrated-circuit die of claim 13,further comprising: first and second corners; wherein the secondconductive pad is located approximately in the first corner; and a thirdconductive pad located in the second corner and operable to indicatewhether the probe tip is aligned with the first conductive pad.
 31. Awafer, comprising: a first integrated-circuit die including a firstconductive pad; and a second conductive pad operable to indicate whethera probe tip is aligned with the first conductive pad.
 32. The wafer ofclaim 31 wherein the first-integrated circuit die includes a circuitcoupled to the first conductive pad.
 33. The wafer of claim 31 whereinthe second conductive pad is disposed on the first integrated-circuitdie.
 34. The wafer of claim 31 wherein the second conductive pad isdisposed remote from the first integrated-circuit die.
 35. The wafer ofclaim 31, further comprising: a scribe line adjacent to the firstintegrated-circuit die; and wherein the second conductive pad isdisposed in the scribe line.
 36. The wafer of claim 31, furthercomprising a third conductive pad operable to indicate whether the probetip is aligned with the first conductive pad.
 37. The wafer of claim 31,further comprising a third conductive pad coupled to the secondconductive pad and operable to indicate whether the probe tip is alignedwith the first conductive pad.
 38. The wafer of claim 31, furthercomprising: a third conductive pad operable to indicate whether theprobe tip is aligned with the first conductive pad; and a conductorcoupled between the second and third conductive pads.
 39. The wafer ofclaim 31, further comprising: a third conductive pad operable toindicate whether the probe tip is aligned with the first conductive pad;and a diode serially coupled between the second and third conductivepads.
 40. The wafer of claim 31, further comprising: a third conductivepad disposed remote from the first integrated-circuit die and operableto indicate whether the probe tip is aligned with the first conductivepad; and wherein the second conductive pad is disposed on the firstintegrated-circuit die.
 41. The wafer of claim 31, further comprising: athird conductive pad disposed remote from the first integrated-circuitdie and operable to indicate whether the probe tip is aligned with thefirst conductive pad; and wherein the second conductive pad is disposedremote from the first integrated-circuit die.
 42. The wafer of claim 31,further comprising: a second integrated-circuit die; a third conductivepad disposed one the second integrated-circuit die and operable toindicate whether the probe tip is aligned with the first conductive pad;and wherein the second conductive pad is disposed on the firstintegrated-circuit die.
 43. The wafer of claim 31, further comprising: asecond integrated-circuit die; a third conductive pad disposed one thesecond integrated-circuit die, coupled to the second conductive pad, andoperable to indicate whether the probe tip is aligned with the firstconductive pad; and wherein the second conductive pad is disposed on thefirst integrated-circuit die.
 44. The wafer of claim 31, furthercomprising: wherein the first integrated-circuit die includes a firstseal ring coupled to the second conductive pad; a secondintegrated-circuit die including a second seal ring; and a thirdconductive pad coupled to the second seal ring and to the secondconductive pad, and operable to indicate whether the probe tip isaligned with the first conductive pad.
 45. A system, comprising: a firstintegrated-circuit die, including: a first integrated circuit; a firstconductive pad coupled to the integrated circuit; and a secondconductive pad operable to indicate whether a probe tip is aligned withthe first conductive pad; and a second integrated circuit coupled to thefirst integrated circuit.
 46. The system of claim 45 wherein the secondintegrated circuit is disposed on the first integrated-circuit die. 47.The system of claim 45, further comprising: a second integrated-circuitdie; and wherein the second integrated circuit is disposed on the secondintegrated-circuit die.
 48. The system of claim 45 wherein one of thefirst and second integrated circuits comprises a controller.
 49. Amethod, comprising: probing a structure having first and secondconductive pads; and using the second pad to determine whether a firstprobe tip is aligned with the first pad.
 50. The method of claim 49wherein probing the structure comprises probing an integrated-circuitdie.
 51. The method of claim 49 wherein probing the structure comprisesprobing a wafer.
 52. The method of claim 49 wherein using the second padcomprises using the second pad to determine whether the first probe tipis in electrical contact with the first pad.
 53. The method of claim 49wherein using the second pad comprises measuring an electricalcharacteristic of the second pad to determine whether the first probetip is aligned with the first pad.
 54. The method of claim 49 wherein:probing the structure comprises probing the structure having a thirdconductive pad; and using the second pad comprises using the second andthird pads to determine whether the first probe tip is aligned with thefirst pad.
 55. The method of claim 49 wherein: probing the structurecomprises probing the structure having a third conductive pad; and usingthe second pad comprises measuring a voltage across second and thirdprobe tips corresponding to the second and third pads to determinewhether the first probe tip is aligned with the first pad.
 56. Themethod of claim 49 wherein: probing the structure comprises probing thestructure having a third conductive pad; and using the second padcomprises: measuring a voltage across second and third probe tipscorresponding to the second and third pads; and determining that thefirst probe tip is aligned with the first pad if a magnitude of thevoltage is less than a threshold.
 57. The method of claim 49 wherein:probing the structure comprises probing the structure having a thirdconductive pad; and using the second pad comprises: measuring a voltageacross second and third probe tips corresponding to the second and thirdpads; and determining that the first probe tip is misaligned with thefirst pad if a magnitude of the voltage is greater than a threshold.